1. Field
Methods and apparatuses consistent with exemplary embodiments relate to a printed circuit board (PCB), and more particularly, to a PCB having vias and a fine circuit, which are integrally formed, and a PCB manufactured using the same.
2. Description of the Related Art
In recent years, various technologies related to electronic devices and circuit boards have been developed with rapid growth of the electronics industry. In particular, a PCB has exhibited a fine pitch and become small and thin according to the trend of electronic products which are lightweight, thin, short and small.
According to the technical trend as described above, interlayer conduction vias and a fine circuit are integrally formed using a laser trench process method or an imprint method, which are disclosed in Korean Patent Registration No. 10-1109323.
In the manufacturing methods as described above and shown in FIG. 1, a pattern is formed (S10), non-electrolytic copper plating (S20) and electrolytic copper plating (S30) are carried out, and a planarization process (S40) is carried out to form vias and a fine circuit at a PCB.
Hereinafter, the steps of the respective methods according to the related art will be described in detail.
FIGS. 2A-2D show a related art LTP method of manufacturing a PCB having vias and a fine circuit, which are integrally formed, and FIGS. 3A-3D show a related art imprint method of manufacturing a PCB having vias and a fine circuit, which are integrally formed.
In the LTP method, as shown in FIGS. 2A-2D, a surface of a dielectric layer at which a circuit pattern is to be formed is removed using a fine circuit forming device, such as an excimer laser, to form a pattern (FIG. 2A), copper plating (FIGS. 2B and 2C) are carried out to form a metal layer, and a planarization process (FIG. 2D) is carried out to complete a circuit.
In the imprint method, as shown in FIGS. 3A-3D, a circuit pattern to be formed at a substrate is formed at a mold in an embossed state, and the embossed mold is pressed against a dielectric layer of the substrate to transfer the circuit (FIG. 3A). Subsequently, copper plating (FIGS. 3B and 3C) is carried out to form a metal layer, and a planarization process (FIG. 3D) is carried out to complete a circuit.
However, in the related art LTP method of forming the vias and the fine circuit at a PCB in the integrated manner, a portion at which a fine circuit pattern is to be formed is removed, which increases a processing time for a large-sized PCB. In the related art imprint method of forming the vias and the fine circuit at a PCB in the integrated manner, a high-priced mold having vias and a fine circuit formed in an embossed state, which increases manufacturing and processing costs. Also, the lifespan of the high-priced mold may be shortened due to high pressure applied to the mold. Furthermore, in a case in which air is trapped in a rugged portion of the mold, defects may occur. Also, in both the LTP method and the imprint method, a copper plating process is required to form a metal layer, which may result in copper plating defects, thereby restricting productivity.